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Chapter 13: DDR2 SDRAM

R

Reserve FPGA V REF Pins

Five pins in I/O Bank 3 are dedicated as voltage reference inputs, V REF . These pins cannot

be used for general-purpose I/Os in a design. Prohibit the software from using these pins

with the constraints provided in Figure 13-5 .

5i

# Prohibit VREF

CONFIG PROHIBIT

CONFIG PROHIBIT

CONFIG PROHIBIT

CONFIG PROHIBIT

CONFIG PROHIBIT

CONFIG PROHIBIT

CONFIG PROHIBIT

CONFIG PROHIBIT

pins on FPGA I/O Bank 3

= H7;

= J1;

= J8;

= L8;

= N1;

= R6;

= T1;

= T6;

Figure 13-5: UCF Location Constraints for FPGA V REF Pins

Special Layout Recommendations

The Xilinx Memory Interface Generator (MIG) tool, part of the CORE Generator?

software, generates DDR2 SDRAM interfaces for Spartan-3A FPGAs. The MIG

implementation leverages the FPGA’s local clocking resources to capture the DDR2

SDRAM read data. Consequently, there is a close relationship between the memory data

pins (SD_DQ<15:8>, SD_DQ_<7:0>) and their associated strobe signals. The MIG software

automatically assigns pins based on this requirement and the Spartan-3A Starter Kit board

is designed accordingly.

The MIG core for Spartan-3A FPGAs includes a loopback signal to calibrate the read strobe

timing. The loopback signal uses two FPGA pins, labeled SD_LOOP_IN and

SD_LOOP_OUT. For best performance, the length of the loop back trace must be equal to

the clock delay from the FPGA to the memory, plus the strobe delay from the memory back

to the FPGA. Put another way, the loopback trace must be one round trip time to and from

the memory. Also, the loopback signal should be in the center of the data interface pins for

best results, not near the edge or in another FPGA I/O bank. The Spartan-3A Starter Kit

board was designed accordingly.

The UG086: Xilinx Memory Interface Generator (MIG) User Guide provides additional

layout recommendations in Appendix A: “Memory Implementation Guidelines” .

?

?

Memory Interface Generator (MIG)

www.xilinx.com/products/design_resources/mem_corner/index.htm

UG086: Xilinx Memory Interface Generator (MIG) User Guide

Improving Revision ‘C’ Board Performance beyond 266 Mbps

The Spartan-3A Starter Kit board was originally designed to support DDR2 SDRAM

memory interfaces up to 133 MHz, or 266 million bits per second data rate (Mbps). During

MIG system testing, a potential performance bottleneck was identified that hinders

performance beyond 133 MHz. Ferrite beads isolate the DDR2 SDRAM’s voltage reference

and I/O voltage supplies but also limit four-word burst transfers to about 150 MHz.

All testing was performed on Revision ‘C’ boards. Figure 13-6 highlights where to find the

board revision code. On Revision ‘D’ boards and later, the ferrite beads are replaced with 0-

ohm resistors.

116

Spartan-3A FPGA Starter Kit Board User Guide

UG330 (v1.3) June 21, 2007

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